Semiconductor device and method for manufacturing the same

ABSTRACT

In a semiconductor device, a support wall is formed between storage nodes to more effectively prevent leaning of a capacitor, and the storage nodes are formed using a damascene process, which may increase a contact area between each storage node and a storage node contact.

CROSS-REFERENCE TO RELATED APPLICATION

The priority of Korean patent application No. 10-2011-0121695 filed on21 Nov. 2011, the disclosure of which is hereby incorporated in itsentirety by reference, is claimed.

BACKGROUND OF THE INVENTION

Embodiments of the present invention relate to a semiconductor deviceincluding a capacitor and a method for manufacturing the same, and moreparticularly to a semiconductor device and a method for manufacturingthe same, which can more effectively prevent a storage node of acapacitor from leaning and can increase a contact region between astorage node and a contact plug.

Generally, semiconductor devices for memory such as a Dynamic RandomAccess Memory (DRAM) have been designed to retain information such asdata or program instructions.

Typically, a unit cell storing data includes one transistor and onecapacitor. A capacitor contained in a DRAM element or the like includesa storage node, a dielectric layer, and a plate electrode.

In recent times, with the increasing integration of the semiconductordevice, an allowable area per unit cell is reduced, such that manydevelopers and companies are conducting research into varioustechnologies capable of making a capacitor that occupies less surfacearea on a substrate.

A variety of methods have been used to increase capacitance, forexample, a method for employing a dielectric layer having a highdielectric constant, a method for forming a storage node and a plateelectrode that are formed of a metal layer having a high work function,and a method for increasing a surface area of the capacitor.

In order to enlarge the surface area of the capacitor, the height of astorage node needs to be increased. That is, in a semiconductor deviceto which precise critical dimension (CD) technology is applied, in orderto assign capacitance requested by the capacitor within an allowed cellregion, an aspect ratio of the capacitor needs to be increased. However,provided that the aspect ratio of the capacitor is increased, the numberof leaning defects in a capacitor array may be increased, such thatthere is a high possibility of causing a bridge between neighboringstorage nodes.

In addition, the conventional storage node formation method forms aninterlayer insulation film, forms a storage node contact hole by etchinga region in which the storage node is to be formed, and deposits anelectrode material in the contact hole. However, the above-mentionedconventional storage node formation method has some problems. In moredetail, if the aspect ratio of the contact hole is increased, it isdifficult to etch lower portions of the hole. In addition, a contactregion of the contact plug may be smaller than desired, possiblyresulting in increased resistance.

BRIEF SUMMARY OF THE INVENTION

Various embodiments of the present invention are directed to providing asemiconductor device and a method for manufacturing the same thatsubstantially obviate one or more problems due to limitations anddisadvantages of the related art.

Embodiments of the present invention relate to a semiconductor devicefor more effectively preventing a capacitor from leaning and increasinga contact region between a storage node and a storage node contact,resulting in improved capacitance.

In accordance with an aspect of the present invention, a semiconductordevice includes a first storage node, a second storage node spaced apartfrom the first storage node along a first direction, a third storagenode spaced apart from the first storage node along a second directioncrossing the first direction, the first, second and third storage nodesbeing included in a plurality of storage nodes, a support wall locatedbetween the first storage node and the third storage node so as tocontact the first storage node and the second storage node and adielectric layer and a plate electrode disposed in a storage noderegion, and in a space between the first and second storage nodes.

The support wall is formed to have a line-type barrier structurearranged along the first direction.

A width of a lower portion of each of the plurality of storage nodes isgreater than the width of an upper portion of each of the plurality ofstorage nodes.

The storage node has a pillar-type structure in which a width of a lowerportion of each of the plurality of storage nodes is greater than thewidth of an upper portion of each of the plurality of storage nodes.

The support wall is disposed on a first side of the first and secondstorage nodes, the semiconductor device further comprising a secondsupport wall disposed on a second side of the first and second storagenodes opposite to the first side.

In accordance with another aspect of the present invention, asemiconductor device includes a first storage node and a second storagenode spaced apart from each other by a predetermined distance, a supportwall configured to contact sidewalls of the first storage node and thesecond storage node and a dielectric layer and a plate electrode locatedbetween the first storage node and the second storage node.

The support wall is configured to contact one sidewall of each of thefirst storage node and the second storage node. The support wall isformed to contact both sidewalls of each of the first storage node andthe second storage node.

The support wall is formed to have a line-type barrier structurearranged along a first direction.

A width of a lower portion of the first and second storage nodes isgreater than a width of an upper portion of the first and second storagenodes. The storage node has a pillar-type structure in which a width ofa lower portion of the first and second storage nodes is greater thanthe width of an upper portion of the first and second storage nodes.

The support wall is disposed on a first side of the first and secondstorage nodes, and a second support wall is disposed on a second side ofthe first and second storage nodes opposite to the first side.

In accordance with another aspect of the present invention, a method formanufacturing a semiconductor device includes forming a mold layer overa lower structure including a storage node contact, removing linearfirst portions of the mold layer disposed between neighboring storagenode regions along a first direction to form a first space, forming asupport wall in the first space, removing second portions of the moldlayer disposed between the storage node regions along a second directionperpendicular to the first direction to form a second space, forming asacrificial isolation film in the second space, removing third portionsof the mold layer disposed in the storage node region to form a trenchexposing the storage node contact, forming a storage node in the storagenode region, removing the sacrificial isolation film and sequentiallyforming a dielectric layer and a plate electrode over the storage node.

The method may further include, prior to forming the mold layer, formingan etch stop film over the lower structure.

The support wall comprises an insulating material with a lowerselectivity ratio than a material of the mold layer.

The step of forming the storage node includes forming a conductive filmover an inner surface of the trench disposed in the storage node region,forming an insulation film over the conductive film to fill the trenchand etching the conductive film and the insulation film until the moldlayer is exposed, thereby isolating the conductive film.

The step of forming the storage node includes forming a conductive filmin the trench disposed in the storage node region and etching theconductive film until the mold layer is exposed, thereby isolating theconductive film.

It is to be understood that both the foregoing general description andthe following detailed description of the present invention areexemplary and explanatory and are intended to provide furtherexplanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a semiconductor device according to one embodiment ofthe present invention.

FIGS. 2 to 9 illustrate a method for manufacturing a semiconductordevice according to an embodiment of the present invention.

FIG. 10 illustrates a pillar-type storage node according to anotherembodiment of the present invention.

FIG. 11 illustrates a semiconductor device according to anotherembodiment of the present invention.

FIG. 12 illustrates a semiconductor device according to anotherembodiment of the present invention.

FIGS. 13 to 20 illustrate a method for manufacturing the semiconductordevice shown in FIG. 12.

DESCRIPTION OF EMBODIMENTS

Reference will now be made in detail to the embodiments of the presentinvention, examples of which are illustrated in the accompanyingdrawings. Wherever possible, the same reference numbers are usedthroughout the drawings to refer to the same or similar parts. Asemiconductor device and a method for manufacturing the same accordingto embodiments of the present invention will hereinafter be describedwith reference to the appended drawings.

FIG. 1 illustrates a semiconductor device according to one embodiment ofthe present invention. FIG. 1( a) is a plan view illustrating thesemiconductor device, and FIG. 1( b) is a cross-sectional viewillustrating the semiconductor device taken along the line A-A′ of FIG.1( a).

Referring to FIG. 1, an interlayer insulation film 112 is formed over alower structure such as a gate electrode (not shown) and a bit line (notshown), and a storage node contact 114 is formed in the interlayerinsulation film 112. The storage node contact 114 is formed between bitlines (not shown), and is electrically coupled to an active region (notshown) of a substrate. In an embodiment, the storage node contact 114may be electrically connected to an active region (not shown) of asubstrate through a landing plug (not shown) formed between gateelectrodes (not shown).

In the embodiment shown in FIG. 1, a storage node 120 of a capacitor isformed over the storage node contact 114. An etch stop film 116 and asupport wall 118 configured to prevent leaning of the storage node 120are formed between the storage nodes 120.

In an embodiment, storage node 120 disposed between support walls 118may have a square profile as shown in FIG. 1. In other embodiments, thestorage node 120 may have a rectangular profile or a circular profile sothat the storage node 120 is a cylinder. Regardless of the geometricprofile, an embodiment may include node structures that are wider at thebase than the top, as seen in the storage node of FIG. 1. The largerwidth of the base portion of the storage node increases the surface areaavailable to contact a storage node contact 114 disposed beneath thestorage node 120, which may reduce alignment problems and contactresistance between a storage nodes 120 and storage node contacts 114.Because embodiments of the present invention are not made with asingle-stage etching process, the dielectric layer 122 and the plateelectrode 124 can be formed with a sufficient thickness to achieveadequate capacitance in a high aspect ratio capacitor.

The support wall 118 may be a line-type barrier structure formed along afirst direction between storage nodes 120 spaced apart from each otherby a predetermined distance. Although the support wall 118 may be formedto contact two sidewalls of the storage node 120 as shown in FIG. 1, inanother embodiment the support wall 118 may be formed to contact onlyone sidewall of the storage node 120.

In addition, the dielectric layer 122 and the plate electrode 124 areformed not only over an outer sidewall of the storage node 120 notcontacting the support wall 118 but also over an inner surface of thestorage node 120, such that capacitor is formed. The plate electrode 124formed over the support wall 118 is not shown in (a) of FIG. 1 for ourconvenience as well as your easy reference.

FIGS. 2 to 9 illustrate a method for manufacturing a semiconductordevice according to an embodiment of the present invention. In each ofFIGS. 2 to 9, (a) is a plan view illustrating the semiconductor device,and (b) is a cross-sectional view illustrating the semiconductor devicetaken along the line A-A′ of each drawing (a).

Referring to FIG. 2, a lower structure that may include a gate electrode(i.e., word line, not shown), a landing plug (not shown), a bit line(not shown), an interlayer insulation film 212, and a storage nodecontact 214, is formed over a device isolation film defining the activeregion. In an embodiment, the storage node contact 214 is formed toexpose its own top surface.

The lower structure may be manufactured using conventional methods, andas such a detailed description thereof will be omitted herein forconvenience of description.

After forming the lower structure, an etch stop film 216 and a moldlayer 218 are sequentially formed over a lower structure in which a topsurface of the storage node contact 214 is exposed. Both of the etchstop film 216 and mold layer 218 may be formed as continuous layers.

In an embodiment, the etch stop film 216 may be formed of a nitridefilm, and the mold layer 218 may be formed of an oxide film. The moldlayer 218 may be formed of BPSG (Boro Phopho Silicate Glass), PSG(Phospho Silicate Glass), TEOS (Tetra Ethyl Ortho Silicate oxide), HDP(High Density Plasma oxide), MTO (Middle Temperature Oxide), HTO (HighTemperature Oxide), USG (Undoped silicate glass), and a silicon film, ora combination thereof.

Next, a photoresist pattern (not shown) defining a linear region (i.e.,a first space region) running along the first direction and disposedbetween the storage node regions, which are denoted by dotted lines inFIG. 2, is formed over the mold layer 218. Subsequently, the mold layer218 is etched until the etch stop film 216 is exposed using thephotoresist pattern as an etch mask, resulting in formation of a trenchT1.

Referring to FIG. 3, an insulation film is formed to fill the trench T1.The insulation film is planarized until mold layer 218 is exposed, sothat a support wall 220 is formed from the insulation film. In anembodiment, the support wall 220 may be formed of a material having anselectivity ratio lower than the material of mold layer 218. Forexample, the support wall 220 may be formed of Si₃N₄, SiBN, or SiCN.

Referring to FIG. 4, the mold layer 218 is etched until the etch stopfilm 216 is exposed. Mold layer 218 may be etched using a line-type mask(not shown) running along a second direction crossing the firstdirection in a space between the storage node regions indicated by thedotted lines of FIG. 3, resulting in trenches (not shown). That is, themold layer 218 of a region (i.e., a second space region) including nosupport wall 220 is selectively removed from spaces between the storagenode regions.

In an embodiment, etching the mold layer 218 may be achieved using aselectivity ratio between the support wall 220 and the mold layer 218.That is, without using a hole mask defining the second space region, themold layer 218 may be selectively removed using a line-type mask. Inanother embodiment, the mold layer 218 may be removed to create thestructure shown in FIG. 4 using a hole mask, where the holes defineareas to be removed.

Referring to FIG. 5, a sacrificial isolation film 222 is formed to filla trench of the second space region.

In an embodiment, the sacrificial isolation film 222 may be formed of amaterial with an selectivity ratio lower than the selectivity ratio ofmold layer 218, and more susceptible to etching than the material usedfor support wall 220. For example, the sacrificial isolation film 222may be formed of silicon, boron-doped silicon, or SiGe.

Subsequently, the mold layer 218 is removed to expose the etch stop film216 using the selectivity ratio between the mold layer 218 and thesupport wall 220, and a selectivity ratio between mold layer 218 and thesacrificial isolation film 222, resulting in formation of a trench T2.In an embodiment, mold layer 218 is removed by a dip out process. Aresulting width of a lower portion of trench T2 may be larger than awidth of an upper portion of the trench. That is, in an embodiment, thestorage node region of the mold layer 218 is not etched as a hole type,but the support wall 220 and the sacrificial isolation film 222 arefirstly formed in the space region using a damascene process, and themold layer 218 of the storage node region is then removed using theselectivity ratio.

In the related art, a lower portion of storage nodes has become smallerin response to the increasing aspect ratio of the storage node. As thesize of the lower portions is reduced, deposition gas is insufficientlytransmitted when forming the dielectric layer and the plate electrode,such that the dielectric layer and the plate electrode are defective. Asa result, conventional techniques may have unacceptably high defectrates above a certain aspect ratio.

However, by using a damascene process according to embodiments of thepresent invention, a sufficient-sized hole CD of the lower part of thestorage node can be obtained, resulting in formation of a stablestructure with adequate capacitance at high aspect ratios.

Referring to FIG. 6, the etch stop film 216 exposed through the trenchT2 is removed such that storage node contact 214 is exposed. In anembodiment, the etch stop film 216 may be removed by a dry etchingprocess.

Subsequently, in an embodiment where the storage node contact 214 isformed of a low conductivity material such as polysilicon, in order toreduce contact resistance between the storage node to be formed in asubsequent process and the storage node contact 214, titanium (Ti) maybe deposited on the exposed storage node contact 214 using a method suchas Chemical Vapor Deposition (CVD). Thermal processing may then beapplied, such that a TiSix film is formed. In an embodiment, if thestorage node contact 214 is formed of metal, the step of forming theTiSix film may be omitted.

Referring to FIG. 7, the conductive film 224 to be used as a storagenode of the capacitor is formed over inner surfaces of the trench T2including the lower surface of the trench, so that the conductive film224 is electrically coupled to storage node contact 214. For example, atitanium nitride (TiN) film may be deposited over an inner surface usingthe CVD method. In an embodiment, as discussed above, a layer of TiSixmay be present between the storage node contact 214 and the conductivefilm 224.

Then, an insulation film 226 is formed over a conductive film 224,filling the trench T2. Next, the insulation film 226 and the conductivefilm 224 are etched and/or planarized using an etchback process, CMPprocess, or a similar technique until the support wall 220 is exposed,such that the conductive film 224 in a capacitor is isolated from theconductive film 224 of neighboring capacitors by removing an upperportion of the film that may remain over an upper surface of supportwall 220. The resultant isolated conductive film 224 serves as anelectrode of a storage node. In an embodiment, the insulation film 226may be an oxide film.

Referring to FIG. 8, the sacrificial isolation film 222 formed in thesecond space region is removed. In an embodiment, the sacrificialisolation film 222 is removed by a wet dip process.

Referring to FIG. 9, the insulation film 226 formed over the conductivefilm 224 is removed. In an embodiment, the insulation film 226 isremoved by a wet dip process. Subsequently, a dielectric layer 228 isdeposited over exposed portions of conductive film 224, for example byusing an Atomic Layer Deposition (ALD) process. As shown in FIG. 9,dielectric layer 228 is formed over all exposed surfaces, including alower surface and sidewalls of the hole, as well as over an uppersurface of support wall 220 between neighboring capacitors. In variousembodiments, dielectric layer 228 may be formed of a dielectric materialsuch as barium strontium (BST), Ta₂O₅, Al₂O₃, HfO₂, or the like.

Then, a conductive film such as a TiN film is formed over the dielectriclayer 228, resulting in formation of a plate electrode 230. The plateelectrode 230 formed over the support wall 220 is not shown in (a) ofFIG. 9 for our convenience as well as your easy reference.

As can be seen from FIG. 7, a conductive film is deposited to apredetermined thickness over an inner surface of the trench T2 in such amanner that the conductive film contacts the storage node contact 214,thereby forming a storage node. However, in an embodiment, a conductivefilm is formed to fill the trench T2 to form a pillar-type storage nodein which a width of a lower portion is larger than a width of an upperportion as shown in FIG. 10.

As used herein, the term “pillar-type” refers to the shape of a storagenode. A pillar-type storage node is characterized by a lower electrodewhich protrudes outward from a surface of a semiconductor, so that itgenerally resembles a pillar. An exemplary pillar-type structure can beseen in FIG. 10. In contrast, other embodiments may be “concave-type.”

As used herein, the term “concave-type” also refers to the shape of thelower electrode. A concave-type electrode can be described as anindented, or female electrode in contrast to a protruding malepillar-type electrode. A lower electrode of a typical concave-typeelectrode is characterized by thin walls disposed over inner surfaces ofa trench or cavity. The lower electrode of a concave-type storage nodegenerally resembles a concavity in a surface of a semiconductor.Exemplary concave-type structures are shown in FIG. 1, FIG. 11, and FIG.20.

FIG. 10 illustrates a pillar-type storage node according to anotherembodiment of the present invention. FIG. 10( a) is a plan viewillustrating another embodiment of the present invention, FIG. 10( b) isa cross-sectional view taken along the line A-A′ of FIG. 10( a), andFIG. 10( c) is a cross-sectional view taken along the line B-B′ of FIG.10( a). A dielectric layer 228′ and a plate electrode 230 formed over astorage node 224′ are not shown in (a) of FIG. 10 for our convenience aswell as your easy reference.

If the storage node is formed as a pillar-type structure, the dielectriclayer 228′ may be formed only on the upper surface and two sidewalls oflower electrode 224′, such that capacitance may be lower than aconcave-type storage node because of the lower surface area. However,the pillar-type storage node has a lower possibility of leaning so thatthe support wall 220′ can be formed to have a width smaller than that ofthe support wall 220. Accordingly, a width of the storage node 224′ canbe increased, resulting in increased capacitance.

FIG. 11 illustrates a semiconductor device according to anotherembodiment of the present invention. The dielectric layer 122 is formedover inner and outer surfaces of the storage node 120 in FIG. 1,resulting in formation of a cylindrical capacitor. However, in anembodiment, the dielectric layer 122′ is formed only over an innersurface of the storage node 120′ as shown in FIG. 11, so that aconcave-type capacitor may be formed. If the capacitor is formed in aconcave shape, a support wall 118′ may be formed to enclose a storagenode 120′. Therefore, in comparison with FIG. 1, a support layer 118′may be formed to have a smaller thickness than the support wall 118, sothat a storage node 120′ is formed to have a wider width than thestorage node of the embodiment shown in FIG. 1. In such an embodiment,support walls 118′ may include crossing lines in both the first andsecond directions, forming a matrix or mesh shape around capacitors.

A method for forming the semiconductor device shown in FIG. 11 isidentical to those of FIGS. 2 to 4, and a first space region and asecond space region are reduced in size. In FIG. 5, the trench of thesecond space region is buried with the same material as the support wall220 instead of the sacrificial isolation film 222. Subsequently, afterthe conductive film 224 is formed at an inner surface of the trench T2as shown in FIGS. 6 and 7, the dielectric layer 228 and the platestorage 230 are sequentially formed over the storage node.

FIG. 12 illustrates a semiconductor device according to anotherembodiment of the present invention. FIG. 12( a) is a plan viewillustrating the exemplary semiconductor device, and FIG. 12( b) is across-sectional view illustrating the semiconductor device taken alongthe line A-A′ of FIG. 12( a).

In comparison with the embodiment shown in FIG. 1, a support wall 318 ofthe embodiment shown in FIG. 12 is formed only on one side of storagenode 320.

In an embodiment, a dielectric layer 322 and a plate electrode 324formed over an outer wall of the storage node 320 are formed to enclosethree sides of the storage node 320, so that capacitance of theembodiment shown in FIG. 12 is increased compared to the embodiment ofFIG. 1. The plate electrode 324 formed over the support wall 318 is notshown in (a) of FIG. 12 for our convenience as well as your easyreference.

An interlayer insulation film 312, a storage node contact 314, and theetch stop film 316 shown in FIG. 12 may be the same as those shown inFIG. 1.

FIGS. 13 to 20 illustrate a method for manufacturing the embodiment ofthe semiconductor device shown in FIG. 12. In FIGS. 13 to 20, (a) is aplan view illustrating a semiconductor device, and (b) is across-sectional view illustrating the semiconductor device taken alongthe line A-A′. The semiconductor device fabrication processes shown inFIGS. 13 to 20 is similar to those of FIGS. 2 to 9. For convenience ofdescription and better understanding of the present invention, thefollowing description omits certain aspects of an exemplary method whichare the same as those of FIGS. 2 to 9, and focuses on the differencesbetween the methods.

Referring to FIG. 13, a lower structure that includes a gate electrode(i.e., word line, not shown), a landing plug (not shown), a bit line(not shown), an interlayer insulation film 412, and a storage nodecontact 414, is formed over a semiconductor substrate (not shown)including a device isolation film defining the active region. In anembodiment, the storage node contact 414 is formed to expose its own topsurface.

Subsequently, an etch stop film 416 and a mold layer 418 aresequentially formed over a lower structure in which a top surface of thestorage node contact 414 is exposed.

After that, a photoresist pattern (not shown) defining a specific region(i.e., a third space region) located on one side of the storage node isformed over a mold layer 418. The photoresist pattern is formed alongthe first direction, and defines spaces between neighboring rows ofstorage nodes which are formed in subsequent steps. The future locationof the storage nodes is shown in by the dotted lines in FIG. 13. Whilethe first space region shown in embodiment of FIG. 2 is formed to definespace regions located on both sides of a row of storage nodes, in theembodiment of FIG. 13, the third space region is formed to define aspace region located only on one side of each row of storage nodes.

Subsequently, the mold layer 418 is etched until an etch stop film 416is exposed using the photoresist pattern as an etch mask, resulting information of a trench T3.

Referring to FIG. 14, after an insulation film is formed to bury thetrench T3, the insulation film is planarized until the mold layer 418 isexposed, such that a support wall 420 is formed.

Referring to FIG. 15, a photoresist pattern (not shown), that defines aspecific region (i.e., a fourth space region) is formed over the moldlayer 418 and the support wall 420. Like the photoresist pattern used todefine support wall 318, the present photoresist pattern is arranged inthe first direction on a second side of a row of storage nodes, which isthe side where the support wall 318 is not present. Subsequently, themold layer 418 is etched until an etch stop film 416 is exposed usingthe photoresist pattern as an etch mask so that a trench (not shown) isformed, and a first sacrificial isolation film 422 is formed in thetrench.

A first sacrificial isolation film 422 may be formed of a material whichhas a selectivity ratio that is lower than the selectivity ratio of themold layer 418 and is higher than the selectivity ratio of the supportwall 420. For example, the first sacrificial isolation film 422 may beformed of silicon, boron-doped silicon, or SiGe.

Referring to FIG. 16, the mold layer 418 is etched until the etch stopfilm 416 is exposed. In an embodiment, a mask comprising a line patternrunning in the second direction, which is orthogonal to the firstdirection of the support walls 420, is applied prior to etching, so thatholes are etched rather than lines. That is, a portion of mold layer 418is selectively removed from a region (i.e., fifth space region) disposedbetween areas that will be occupied by storage nodes.

In an embodiment, etching the mold layer 418 in the second space regionmay be achieved using a selectivity ratio between the support wall 420and the mold layer 418. Thus, in an embodiment, second spaces may becreated using line masks and the selectivity ratio, rather than holemasks.

Subsequently, a second sacrificial isolation film 424 is formed to burythe trench of the second space region. In an embodiment, the secondsacrificial isolation film 424 may be formed of the same material as thefirst sacrificial isolation film 422.

Subsequently, remaining portions of mold layer 418 are removed (dippedout) to expose the etch stop film 416 using the selectivity ratiobetween the mold layer 418 and the support wall 420, and selectivityratios between the mold layer 418 and the first sacrificial isolationfilm 422, and the mold layer 418 and the second sacrificial isolationfilm 424, resulting in formation of a trench T4.

Referring to FIG. 17, portions of the etch stop film 416 exposed throughthe trench T4 are removed so that the storage node contact 414 isexposed. In an embodiment, the etch stop film 416 may be removed by adry etching process.

Referring to FIG. 18, the conductive film 426 to be used as an electrodeof the capacitor is formed over inner surfaces of the trench T4including the storage node contact 414.

Then, after an insulation film 428 is formed over the conductive film426 to bury the trench T4, the insulation film 428 and the conductivefilm 426 are etched/planarized using an etchback or CMP process untilthe support wall 420 is exposed, such that the conductive film 426 ofeach storage node is isolated. The resultant isolated conductive filmserves as a second electrode of a storage node. In an embodiment, theinsulation film 428 may be an oxide film.

Referring to FIG. 19, the first sacrificial isolation film 422 formed ina fourth space region and the second sacrificial isolation film 424formed in a fifth space region are removed by a wet dip process.

Referring to FIG. 20, the insulation film 428 is removed by a wet dipprocess. Subsequently, a dielectric layer 430 is deposited over theconductive film 426 using an Atomic Layer Deposition (ALD) process. Thedielectric layer 430 may be formed over all exposed surfaces ofconductive film 426, as well as exposed portions of etch stop 416disposed between neighboring storage nodes, and outer sidewalls of thestorage nodes which are not in contact with support wall 420.

Then, a conductive film is formed over the dielectric layer 430,resulting in formation of a plate electrode 432.

Although the present invention has been disclosed by referring to theabove-mentioned embodiments, it should be noted that the aforementionedembodiments have been disclosed for only illustrative purposes, andthose skilled in the art will appreciate that various modifications,additions and substitutions are possible, without departing from thescope and spirit of the invention as disclosed in the accompanyingclaims. Thus, it is intended that the present invention covers themodifications and variations of this invention provided they come withinthe scope of the appended claims and their equivalents.

As is apparent from the above description, embodiments of the presentinvention form a support wall between storage nodes to prevent acapacitor from leaning, and form storage nodes using a damasceneprocess, such that a contact area between each storage node and astorage node contact is increased, thereby reducing resistance andalignment problems.

The above embodiments of the present invention are illustrative and notlimitative. Various alternatives and equivalents are possible. Theinvention is not limited by the type of deposition, etching polishing,and patterning steps described herein. Nor is the invention limited toany specific type of semiconductor device. For example, the presentinvention may be implemented in a dynamic random access memory (DRAM)device or non volatile memory device. Other additions, subtractions, ormodifications are obvious in view of the present disclosure and areintended to fall within the scope of the appended claims.

1. A semiconductor device comprising: a first storage node; a secondstorage node spaced apart from the first storage node along a firstdirection; a third storage node spaced apart from the first storage nodealong a second direction crossing the first direction, the first, secondand third storage nodes being included in a plurality of storage nodes;a support wall located between the first storage node and the thirdstorage node so as to contact the first storage node and the secondstorage node; and a dielectric layer and a plate electrode disposed in astorage node region, and in a space between the first and second storagenodes.
 2. The semiconductor device according to claim 1, wherein thesupport wall is formed to have a line-type barrier structure arrangedalong the first direction.
 3. The semiconductor device according toclaim 1, wherein a width of a lower portion of each of the plurality ofstorage nodes is greater than the width of an upper portion of each ofthe plurality of storage nodes.
 4. The semiconductor device according toclaim 1, wherein the storage node has a pillar-type structure in which awidth of a lower portion of each of the plurality of storage nodes isgreater than the width of an upper portion of each of the plurality ofstorage nodes.
 5. The semiconductor device according to claim 1, whereinthe support wall is disposed on a first side of the first and secondstorage nodes, the semiconductor device further comprising a secondsupport wall disposed on a second side of the first and second storagenodes opposite to the first side.
 6. A semiconductor device comprising:a first storage node and a second storage node spaced apart from eachother by a predetermined distance; a support wall configured to contactsidewalls of the first storage node and the second storage node; and adielectric layer and a plate electrode located between the first storagenode and the second storage node.
 7. The semiconductor device accordingto claim 6, wherein the support wall is configured to contact onesidewall of each of the first storage node and the second storage node.8. The semiconductor device according to claim 6, wherein the supportwall contacts two sidewalls of each of the first storage node and thesecond storage node.
 9. The semiconductor device according to claim 6,wherein the support wall has a line-type barrier structure arrangedalong a first direction.
 10. The semiconductor device according to claim6, wherein a width of a lower portion of the first and second storagenodes is greater than a width of an upper portion of the first andsecond storage nodes.
 11. The semiconductor device according to claim 6,wherein the storage node has a pillar-type structure in which a width ofa lower portion of the first and second storage nodes is greater thanthe width of an upper portion of the first and second storage nodes. 12.The semiconductor device according to claim 6, wherein the support wallis disposed on a first side of the first and second storage nodes, and asecond support wall is disposed on a second side of the first and secondstorage nodes opposite to the first side. 13-18. (canceled)